1. Field of the Invention
The present invention generally relates to differential output circuits and semiconductor devices, and more particularly to a differential output circuit that is used in a driver circuit for a high-speed low-amplitude differential output interface, and to a semiconductor device having such a differential output circuit.
2. Description of the Related Art
Conventionally, differential output circuits used in driver circuits for high-speed low-amplitude differential output interfaces include Current Mode Logic (CML) circuits shown in FIGS. 1 and 2 and Low Voltage Difference Signaling (LVDS) circuits such as that shown in FIG. 3. In cases where such differential output circuits are used in driver circuits of semiconductor integrated circuits such as ICs and LSIs for high-speed signal transmission apparatuses as shown in FIGS. 4 through 6, an output signal must be output from the differential output circuit to the outside of the differential output circuit. For this reason, input/output cells including pad portions that connect to terminals of an IC package via wires are connected to an output part of the differential output circuit. In such input/output cells, a protection element or a protection circuit is used to prevent deterioration or damage to the semiconductor integrated circuit caused by surge or Electro-Static Discharge (ESD).
In FIGS. 1 through 6, the same designations are used for the circuit elements. VCC1 and VCC2 denote power supplies or power supply voltages, GND denotes the ground or ground voltage, and VA and VB denote control inputs.
FIGS. 4 and 5 show cases where the input/output cells are connected to the CML circuit shown in FIG. 2 using N-channel MOS transistors (hereinafter simply referred to as NMOS transistors) as differential pair transistors.
In FIGS. 4 and 5, NMOS transistors N1 and N2 forming the differential input pair respectively operate in response to corresponding input signals Si1 and Si2, and a current flowing through an NMOS transistor N3 that forms a current source flows to one of the NMOS transistors N1 and N2. The input signals Si1 and Si2 are logic signals having mutually inverted logic signal levels. Output signal So1 and So2 that are output from corresponding first and second output terminals OUT1 and OUT2 respectively have amplitudes determined by currents flowing through corresponding resistors R1 and R2 and resistances of these resistors R1 and R2.
In FIG. 4, the resistors R1 and R2 are externally connected to the corresponding first and second output terminals OUT1 and OUT2, and are connected to a power supply VCC2 which is different from an internal power supply VCC1. But if the internal power supply VCC1 can be used, it is possible to use it as a common power supply instead of using the two power supplies VCC1 and VCC2.
In FIG. 5, the resistors R1 and R2 are internally connected to the corresponding first and second output terminals OUT1 and OUT2, and are connected to the internal power supply VCC1. However, it is possible to use a different power supply VCC2 in place of the internal power supply VCC1.
FIG. 6 shows a case where the input/output cells are connected to the LVDS circuit shown in FIG. 3 using N-channel MOS transistors as differential pair transistors and P-channel MOS transistors (hereinafter simply referred to as PMOS transistors) as differential pair transistors.
In FIG. 6, NMOS transistors N1 and N2 forming the differential pair respectively operate in response to corresponding input signals Si1 and Si2, and PMOS transistors P1 and P2 forming the differential pair respectively operate in response to the corresponding input signals Si1 and Si2. A current flowing through an NMOS transistor N3 that forms a current source flows to one of the NMOS transistors N1 and N2 or, a current flowing through a PMOS transistor P3 that forms a current source flows to one of the PMOS transistors P1 and P2.
Generally, the input signals Si1 and Si2 have logic levels such that the current flows to the PMOS transistor P2 when the current flows through the NMOS transistor N1, and the current flows to the PMOS transistor P1 when the current flows through the NMOS transistor N2. The current flowing through the PMOS transistor P3 and the current flowing through the NMOS transistor N3 have approximately the same current values.
The output signals So1 and So2 that are output from the corresponding first and second output terminals OUT1 and OUT2 have amplitudes determined by the voltage generated by the current flowing through a resistor R4 that is connected between the first and second output terminals OUT1 and OUT2.
FIG. 7 is a circuit diagram showing an example of a conventional low-amplitude differential output circuit applied with the case shown in FIG. 4. In FIG. 7, a first power supply voltage is the ground voltage GND, a second power supply voltage is VCC1, and a third power supply voltage is VCC2.
A low-amplitude differential output circuit 100 shown in FIG. 7 includes NMOS transistors N1 and N2 forming a differential pair, resistors R1 and R2 forming loads of the corresponding NMOS transistors N1 and N2, a constant current circuit 101 for supplying a predetermined constant current to the NMOS transistors N1 and N2, and an input control circuit 102 for generating signals Si1 and Si2 having mutually inverted logic levels (or complementary logic signal levels) based on an input signal Si which is a logic signal.
The input logic signal Si that is input to the low-amplitude differential output circuit 100 is converted into the 2 kinds of logic signals Si1 and Si2 having the mutually inverted logic signal levels by the input control circuit 102, and the logic signals Si1 and Si2 are input to the gates of the corresponding NMOS transistors N1 and N2 forming the differential pair.
The constant current circuit 101 carries out a current conversion with respect to an external reference voltage V1 via an operational amplifier AMP, a resistor, a PMOS transistor P11 and an NMOS transistor N11. Since the reference voltage V1 is stable, a constant current is obtained by this current conversion. The constant current is supplied to the NMOS transistors N1 and N2 via PMOS transistors P11 and P12 forming a current mirror circuit and NMOS transistors N3 and N12 forming a current mirror circuit.
The currents flowing through the NMOS transistors N1 and N2 are switched depending on the logic signals Si1 and Si2 from the input control circuit 102. A resistor R1 is connected between a first output terminal OUT1 and the third power supply voltage VCC2, and a resistor R2 is connected between a second output terminal OUT2 and the third power supply voltage VCC2. Amplitudes of output signals So1 and So2 are determined from the currents flowing through the NMOS transistors N1 and N2 and the resistances of the resistors R1 and R2.
Since the first and second output terminals OUT1 and OUT2 are directly connected to an external circuit, input/output cells IO1 and IO2 each including a pad and a protection element for preventing electrostatic damage are connected to the corresponding first and second output terminals OUT1 and OUT2. The circuit elements shown in FIG. 7, excluding the resistors R1 and R2, are integrated within a single IC.
For example, a Japanese Patent No. 3202196 (issued from a Japanese Laid-Open Patent Application No. 2000-68813) proposes providing in parallel transistors forming a differential input pair of the differential output circuit and transistors having the sources thereof connected in common, so that the transistors operate during a normal operation of the differential output circuit.
A Japanese Laid-Open Patent Application No. 2004-215137 proposes providing in parallel to an input transistor pair of the differential output circuit transistors for amplifying a high-frequency component.
A Japanese Laid-Open Patent Application No. 2004-31407 proposes a CML circuit using 2 circuits having the same structure as a countermeasure against inconsistencies introduced during the production process of the differential output circuit.
A Japanese Laid-Open Patent Application No. 2004-112453 proposes a transmission apparatus operating at low voltages.
Recently, in high-speed interfaces, there are demands to increase the operation speed of the low-amplitude differential output circuit. In the case of the circuit shown in FIG. 7, the input/output cells IO1 and IO2 for preventing electrostatic damage are connected to the corresponding first and second output terminals OUT1 and OUT2 which form differential output terminals. For this reason, as the operation speed of the low-amplitude differential output circuit increases, the operation speed deteriorates due to the effects of the protection element within the input/output cells IO1 and IO2 and the effects of a parasitic element in the vicinity of the protection element.
As for the quality of the differential output, an error is generated in the waveform of the differential output from the first and second output terminals OUT1 and OUT2 due to inconsistencies, generated during the production process, of the internal cells and the parasitic elements in the vicinity of the internal cells, between the input/output cells IO1 and IO2 that are connected to the corresponding first and second output terminals OUT1 and OUT2.
In an integrated circuit having a large scale as in the case of the LSI, the scale of the circuit and functions within the circuit is large, and a large number of input/output cells are used because the package has a large number of terminals or pads for the integrated circuit. Accordingly, when using the low-amplitude differential output circuit shown in FIG. 7 in the integrated circuit, it is necessary to develop special input/output cells that are different from peripheral input/output cells, as the input/output cells for the driver circuit. Consequently, in addition to the time required to develop the internal circuits to be provided in the integrated circuit, additionally time is required to develop the special input/output cells.
Generally, a resistor or a transistor is used as the protection element for preventing the electrostatic damage. But when the transistor is used as the protection element, the transistor and the parasitic element in the vicinity of the transistor affect the high-speed characteristic of the integrated circuit. When a resistor is connected between the pad and each output terminal producing the differential output of the low-amplitude differential output circuit, the high-speed characteristic of the low-amplitude differential output circuit is affected by the parasitic element in the vicinity of the resistor and the increase in circuit area caused by the provision of the resistor. In addition, in the case of the circuit shown in FIG. 7, the connection of the resistor reduces a drain-source current of the NMOS transistor N3 forming the current mirror circuit, and the constant current characteristic of the constant current circuit 101 deteriorates because the operation of the NMOS transistor N3 changes from a 5-active (or 5-saturation) region operation to a 3-active (or 3-saturation) region operation.
In addition, in a case where a resistor is connected between the pad and the output terminal for improving ESD withstand voltage, the circuit area increases due to the additional provision of the resistor, and the operation speed deteriorates due to the resistor and the parasitic element. As for the operation of the internal circuit, the operating range of the transistor within the differential output circuit decreases due to the additional provision of the resistor. For example, if the NMOS transistor N3 and the PMOS transistor P3 shown in FIGS. 4 through 7 form a current mirror circuit together with an external constant current circuit, a source-drain voltage for operating the NMOS transistor N3 and the PMOS transistor P3 in the 5-active (or 5-saturation) region is required, and in order to increase the source-drain voltage that is reduced due to the additional provision of the resistor, it is necessary to increase the transistor size of the NMOS transistor N3 and the PMOS transistor P3. Consequently, the circuit area increases in such a case.
Furthermore, the so-called silicide transistor having a thin oxide layer and reduced parasitic resistance in the periphery of the transistor is used to further improve the high-speed operation. On the other hand, such a silicide transistor is not used, and instead, a transistor having a thick oxide layer is used for the transistor within the input/output cell where the electrostatic and surge directly enter.
However, when the electrostatic or surge enters the input/output cell from the outside, the electrostatic or surge may not pass through the input/output cell and deteriorate the silicide transistor which has the thin oxide layer and the reduced parasitic resistance within the integrated circuit. Particularly the low-amplitude differential output circuit is easily affected by such electrostatic or surge, because the output part is directly connected to the pad.
Therefore, it is conceivable to increase the transistor size of the protection transistor which is provided within the input/output cell for the purpose of improving the ESD withstand voltage, so that the electrostatic or surge passes through the input/output cell. However, increasing the transistor size of the protection transistor will increase the parasitic resistance in the periphery of the protection transistor, to thereby cause the high-speed operation of the low-amplitude differential output circuit to deteriorate.